1. Field of the Invention
The present invention relates to a counter circuit, and more particularly, to a counter circuit using a Johnson-type counter and to applications thereof.
The counter circuit and its applied circuits according to the present invention can be utilized in various digital applied circuits which frequently need operations for converting a chain of serial data into parallel data of a plurality of bits, or converting parallel data of a plurality of bits into a chain of serial data.
2. Description of the Related Art
With a recent demand for high speed operation of various digital applied circuits or systems, a development of integrated circuits (IC) which can effect perform signal processing with high speed has been, demanded. To this end, it is necessary to achieve high speed operations of the individual, respective circuits within the IC.
As an example of a counter circuit using a Johnson-type counter, a 1/N frequency-dividing circuit including a plurality of flip-flops connected in a cascade connection is known. In this constitution, the first stage flip-flop receives a clock signal and the last stage flip-flop outputs a 1/N divided signal. Accordingly, the 1/N divided signal cannot be obtained until the clock signal is applied and then passed through the flip-flops of the plurality of stages. Namely, it takes considerable time, corresponding to an operation delay time of the flip-flops, to obtain the 1/N divided signal. This is disadvantageous from a viewpoint of the operation speed.
Also, since the flip-flops are connected in a cascading manner, drawback arises in that the ratio of frequency division is fixed depending on the number of flip-flops used.
As another example of a counter circuit using a Johnson-type counter, a divided signal generating circuit effecting a logical-OR operation is known. In this case, each signal input to the OR logic portion needs an input amplitude of a predetermined level. However, when the input amplitude is increased, a problem occurs in that the operation delay time of each, flip-flop is prolonged. This leads to a lowering of the maximum operating frequency of the Johnson-type counter and therefore, make this type of counter circuit undesirable.
The problems in the prior art will be explained later in detail in contrast with the preferred embodiments of the present invention.